1. AI AND MACHINE LEARNING

• Improving productivity and achieving faster quality of results with AI and machine learning in Synopsys design flows
• From the data center to the edge – enabling highest performance AI designs with Synopsys implementation solutions
• Architectural exploration and early software development with virtual/physical prototyping
• Formal verification of data path designs
• Using emulation for AI software stack validation
• AI-enabled productivity and performance innovation
• Using virtual test environments for network system validation
• Using AI-ready IP to meet processing, memory, and connectivity requirements for deep learning applications
• The challenges of designing and integrating AI accelerators

2. AUTOMOTIVE

• Accelerating automotive software development and validation with virtual prototyping
• Complete functional safety verification with fault simulation, formal and static verification
• High-reliability design techniques for automotive designs
• Hardware security verification
• Implementing safety critical designs for automotive applications
• Designing ISO 26262 required in-system test using Synopsys tools
• Accelerating ISO 26262 certification with ASIL-ready certified IP

3. ANALOG/MIXED-SIGNAL DESIGN AND SIMULATION   

• Addressing analog, custom digital or memory design verification turnaround time bottlenecks with heterogenous compute acceleration
• RF analysis of RFIC or analog periodic circuits using FineSim
• Ensuring AMS design robustness with advanced variability analysis
• Minimizing design margins with integrated power/signal net electromigration/IR drop analysis
• Improving AMS design robustness with analog circuit ERC
• Best practices in mixed-signal verification with a digital verification methodology using CustomSim and VCS
• Verifying power and signal integrity for multi-gigabit circuits with HSPICE
• Accelerating pre-layout design centering & optimization
• Custom layout productivity gains from using Custom Compiler’s visually assisted automation (symbolic editor, interactive routing, template-based design)
• Mixed custom/digital implementation productivity gains from using Custom Compiler co-design with IC Compiler II or Fusion Compiler
• Faster analog design closure using Custom Compiler early electrical analysis with StarRC (in-design RC and EM, partial-layout simulation flow)

4. DESIGN AND VERIFICATION IN THE CLOUD

• Trading off performance vs. cost for design or verification in a cloud environment
• Security concerns and best practices in migrating from on-premises to cloud for design and verification
• Allocation and usage of cloud resources for library characterization, simulation, timing analysis and parasitic extraction
• Maximizing available resources with ICV elastic CPU usage
• Impacts on design size partition for physical implementation in a cloud environment
• Leveraging tool runtime scalability in the cloud; what worked best

5. DIGITAL DESIGN IMPLEMENTATION

• Raising the bar on achieved PPA with a Fusion Compiler convergent flow
• Optimal design flow for digital implementation of advanced node designs
• Accelerating time to results for large designs with Design Compiler Graphical and IC Compiler II
• Shift-left convergence with RTL Architect by improving constraints and RTL restructuring
• How to achieve optimized performance, power and area for Arm CPUs
• Using parallel processing to accelerate physical and full-chip timing signoff
• Accelerating full-chip turnaround time for large designs using IC Validator physical signoff
• Optimization techniques for low-power IoT designs
• Early time-based peak power analysis with PrimePower using RTL-based vectors
• Using  physically aware ECO capabilities to improve PPA and accelerate timing closure
• Design implementation on the cloud
• Extending the envelope of Moore’s law with multi-die design

6. ENERGY-EFFICIENT SoCs

• Low-power design for smart edge devices
• AI-driven power considerations
• The quest for energy efficiency: evaluating hardware and software approaches
• Transistor-level vs. system-level energy optimization
• Is Low Low Enough? The Special Power Demands of Crypto Chips

7. MULTI-DIE

• Enabling next-generation HPC designs with multi-die design and methodology
• Multi-die architectural planning and chip-package co-design
• Delivering multi-die Innovations to power the Era of SysMoore
• Golden parasitic extraction and signoff analysis for multi-die designs

8. MEMORY

Design Technology Co-optimization:

• Memory technology exploration (novel devices, process recipes) with TCAD and SPICE
• Memory technology pathfinding with virtual PDKs
• Faster design closure with In-design lithography rule checking using Custom Compiler

Design Shift Left:

• Faster block/chip-level simulation TAT
• Faster PDN simulation with heterogenous compute (CPU + GPU) acceleration
• ML-driven high sigma Monte Carlo analysis for library characterization
• Faster physical verification on memory designs with ML-driven scheduling and distributed processing
• Faster design closure with pre-layout parasitic estimation
• Higher productivity with Co-design & multi-die design for 2.5D/3D memory devices

Digitization:

• Mixed-signal verification flows for memory data path
• Static timing analysis for embedded memories
• Timing robustness with MOS aging-aware static timing analysis
• Automated place & route for memory periphery

Silicon Reliability:

• Higher coverage with circuit ERC
• Fast chip-level EM/IR analysis w/ PDN
• Functional safety analysis and ISO 26262 compliance for memory IP with analog defect simulation
• Analog test coverage improvement with analog defect simulation
• Faster silicon failure analysis with analog defect simulation
• Silicon lifecycle management for memory IP
• Memory protocol verification and coverage closure

9. PHYSICAL VERIFICATION

• Leveraging ICV multi-CPU scalability for fast time-to-results
• Maximizing available resources with ICV elastic CPU usage
• Dirty design handling during SoC integration to minimize runtime and maximize productivity
• Shift-left physical verification analysis and repair utilizing fusion technology in IC Compiler II and Fusion Compiler

10. SECURITY, GOVERNMENT & AEROSPACE

• Strategies to Reduce Chip Vulnerabilities Through Hardware, IP or Software Approaches
• The Role of an SoC-based Root of Trust for Security
• How to Leverage Standards to Enhance Safety and Security
• Hardware and Software Approaches to Implementing Functional Safety

11. SIGNOFF

• How 3DIC design changes signoff
• AI algorithms and their impact on signoff
• Balancing timing, power, power/signal integrity closure

12. SILICON TEST AND LIFECYCLE MANAGEMENT

• Success with early RTL analysis, physically aware and area-saving DFT, higher defect detection, lower pattern count/test time, faster and volume diagnostics
• Use of software analytics for accelerating product introduction as well as improving yield, test times and quality during high-volume production
• Highlighted SoC application areas include AI, automotive, mobile and processors

13. SUCCESSFUL IP INTEGRATION INTO SoCs

• Interface IP such as 112G Ethernet, Die-to-Die, PCIe 5.0, DDR5/LPDDR5, etc.
• Embedded ARC processors & embedded vision processors
• OTP NVM, embedded memories & logic libraries in advanced FinFET processes
• Integration of IP into high-performance computing, automotive, AI/ML or IoT designs
• Integration of PVT sensor IP monitors and subsystems for enhanced device screening, power and performance optimization, and enhanced field performance/security

14. VERIFICATION HARDWARE

• Accelerating software bring-up with emulation and prototyping
• Software-driven power analysis for GPUs and AI
• Prototyping with real-world interfaces
• Large complexity prototyping
• Pre-silicon networking system validation
• SoC performance validation using emulation
• Trust and hardware security verification
• DFT-driven emulation
• The value of emulation for mission-critical designs
• Insights from power emulation
• Prototyping approaches for 2.5D/3D heterogeneous integration
• The insights available from prototyping

15. VERIFICATION SOFTWARE

• Faster and better convergence using formal methods
• Verification coverage planning and closure
• Best practices for static verification (Lint/CDC/RDC/SDC/LP) signoff
• Accelerating verification and debug for advanced protocols
• Innovations in verification methodology for optimized performance